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RM0008
Analog-to-digital converter (ADC)
Figure 34. Regular simultaneous mode on 16 channels
Sampling
Conversion
ADC1
ADC2
CH0
CH15
CH1
CH14
CH2
CH13
CH3
CH12
...
...
CH15
CH0
Trigger
End of conversion on ADC1 and ADC2
11.9.3
Fast interleaved mode
This mode can be started only on a regular channel group (usually one channel). The
source of external trigger comes from the regular channel mux of ADC1. After an external
trigger occurs:
●
●
ADC2 starts immediately and
ADC1 starts after a delay of 7 ADC clock cycles.
If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are
continuously converted.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
Note:
The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between
ADC1 and ADC2 sampling phases in the event that they convert the same channel.
Figure 35. Fast interleaved mode on 1 channel in continuous conversion mode
End of conversion on ADC2
Sampling
Conversion
ADC2
ADC1
CH0
...
CH0
...
C H 0
CH0
Trigger
7 ADCCLK
cycles
End of conversion on ADC1
11.9.4
Slow interleaved mode
This mode can be started only on a regular channel group (only one channel). The source of
external trigger comes from regular channel mux of ADC1. After external trigger occurs:
●
●
●
ADC2 starts immediately and
ADC1 starts after a delay of 14 ADC clock cycles.
ADC2 starts after a second delay of 14 ADC cycles, and so on.
Note:
The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the
next conversion.
Doc ID 13902 Rev 9
213/995
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